Impact of Device Parameter Variation on the Electrical Characteristic of N-type Junctionless Nanowire Transistor with High-k Dielectrics

Received Jan 7, 2020 Revised June 28, 2020 Accepted June 30, 2020 Metallurgical junction and thermal budget are serious constraints in scaling and performance of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). To overcome this problem, junctionless nanowire fieldeffect transistor (JLNWFET) was introduced. In this paper, we investigate the impact of device parameter variation on the performance of n-type JLNWFET with high-k dielectrics. The electrical characteristic of JLNWFET and the inversion-mode transistor of different gate length (LG) and nanowire diameter (dNW) was compared and analyzed. Different high-k dielectrics were used to get an optimum device structure of JLNWFET. The device was simulated using SDE Tool of Sentaurus TCAD and the I-V characteristics were simulated using Sdevice Tools. Lombardi mobility model and Philips unified mobility model were applied to define its electric field and doping dependent mobility degradation. A thin-film heavily doped silicon nanowire with a gate electrode that controls the flow of current between the source and drain was used. The proposed JLNWFET exhibits high ON-state current (ION) due to the high doping concentration (ND) of 1 x 10 cm which leads to the improved ON-state to OFF-state current ratio (ION/IOFF) of about 10% than the inversionmode device for a LG of 7 nm and the silicon dNW of 6 nm. Electrical characteristics such are drain induced barrier lowering (DIBL) and subthreshold slope (SS) were extracted which leads to low leakage current as well as a high ION/IOFF ratio. The performance was improved by introducing silicon dioxide (SiO2) with high-k dielectric materials, hafnium oxide (HfO2) and silicon nitrate (Si3N4). It was found that JLNWFET with HfO2 exhibits better electrical characteristics and performance.


INTRODUCTION
To speed up the performance of the microprocessor, the number of transistors must be double in every 18 months. To double the number of transistors means to reduce the size of transistor. As what being predicted by Moore's law, process technology tends to be scaled down continuously [1]. The scaling process allowed more transistors to be packed in a smaller chip area and hence enhance the functionality of silicon on chips (SoCs). MOSFET typically used in industries due to its small size, and can be fabricated in a single integrated circuit with millions of numbers. However, the scaling of conventional planar transistor has reached its limit which lead to increase in short channel effects (SCEs) and sensitivity to process variation [2]. SCEs are the main limitations in the scaling of MOSFET below 10nm [3]. SCEs comprises of Drain Induced Barrier Lowering (DIBL), subthreshold slope (SS), limitation imposed on electron drift characteristics in the channel, increase in threshold voltage variation, reduction in ION/IOFF ratio and increase of leakage current causing the scaling of conventional CMOS transistors in sub 10nm technologies almost impossible. This is due to the fact that reduction in ION/IOFF ratio leads to device instability and hence limits subthreshold circuit design. Furthermore, increment in leakage current leads to the static power consumption increment [2]. In PN Junction transistor, the junction is formed when a piece of P-type silicon material and N-type piece of silicon are in contact. The majority carriers in N-type material are electrons, while holes are the majority carriers in P-type semiconductor. Some junction formed by two different semiconductors e.g. Schottky diode, heterojunction etc. Bipolar junction transistor contains two p-n junctions, JFET (junction fieldeffect transistor) has only one p-n junction and MOSFET contains a Schottky junction [4]. Junctionless transistor (JLFET) was introduced to replace the traditional junction transistor because of the challenges in scaling and complex thermal budget of the device [5]. Junctionless transistors can be described as variable resistors controlled by a gate electrode. JLNWFET is a very thin heavily doped semiconductor nanowire that has gate electrode that control the flow of current from source to drain [6]. The gate oxide thickness has gradually decreased so as to increase the gate capacitance as well as to drive the current to increase the device performance [7].Nanowire transistor has a uniform heavily doping concentration from source to drain. The channel also has the same doping concentration that can be fully depleted to turn the device off.High doping concentration and ultra-shallow junction are the main obstacles in improving scaling in MOSFETs [8]. Short channel effects such as Drain Induced Barrier Lowering (DIBL), subthreshold Swing (SS) and so on reduces the performance of the device [9]. Junctionless transistors, also known as gated resistor, have no junctions hence, no doping concentration gradients, simpler fabrication process, diminished DIBL and SS, and better electrical properties. Short channel effects are significantly reduced in Junctionless transistor [10]. The properties of the material of the gate and channel wires in conjunction with the nanoscale geometries in metalgated junctionless FET (MJLFET) allows FET-like switching characteristics without the need for engineered source and drain junctions or lateral doping abruptness [11].
Previous work shows that Many researchers have contributed tremendously in identifying the challenges in scaling of conventional MOSFET. Junctionless FETs were proposed in order to overcome short channel and scaling challenges [12]. JLT exhibits excellent ION-IOFF ratio, improved the scaling to the sub region, decreasing the short channel effects (SCE) and better electrical properties. SCEs can be mitigated by reducing the electrostatic integrity factor which depends on the geometry of the device and it is a measure of the way the electric field lines from drain influence the channel region thus causing the SCEs [13]. Lowsidewalls can improve the SCEs of the device significantly by reducing the fringing-induced barrier lowering for thick-gate insulators [14].
Multigate junctionless transistor (MuGJLT) was compared with MOSFET for a gate length of 10 -30 nm has been conducted by Chi-Woo Lee et al. [9]. The electrical characteristics such as the DIBL, SS and threshold voltage (VTH) of both MuGJLT and MOSFET were evaluated and analyzed. In this study, DIBL and SS of MuGJLT were significantly improving better than the conventional MOSFET for different LG. The SS of the device with LG 5nm is below 80mV/decade which is better than that of the MOSFET. This shows the potential of JLT for extremely short-channel applications. The IOFF is determined entirely by the electrostatic control of the gate not by the leakage current of a reverse-biased diode. The drain current was high due to the high doping concentration of 8 x 10 19 cm -3 and the cross-sectional area of the silicon wire is too small compare to the IM which used lightly doped channel in order to avoid pre-matured inversion at the corners [9].The electrical properties of junctionless nanowire transistor (JNT), inversion-mode transistor and accumulationmode MOS devices for gate length 5nm were compared by J.P. Colinge et al. [15]. The variation of threshold voltage with physical parameters and intrinsic device performed was analyzed.
The drain current IDS was significantly increased even for a gate length of 10 nm, but the leakage current is also high for VGS = 0 V. This shows the leakage current is high in nanowire junctionless transistor having thickness oxide, tox of 2 nm. DIBL and SS were high for short LG, but significant improved when the effective length, Leff was high i.e. when LG is 15 nm achieves a degraded SS of 78 mV/dec and DIBL of 95 mV/V [15]. The electrical characteristics of Nanowire JLFET and core shell JLFET were compared in [16]. IOFF was improved by more than one order of magnitude when a high-k dielectric is used as a spacer in double gate junctionless transistor [17]. The leakage current has reduced due to parasitic bipolar junction transistor (BJT) action in the NWJLFET [18]. Core shell JLFET with the higher doping concentration has the lower leakage current is and therefore, exhibit higher ION/IOFF ratio. Although a core doping of 1 x 10 19 cm -3 depletes the shell region at core shell interface, but the depletion is not sufficient to volume depletion. Electron channel still exists in the channel region. Highly doped p+ core of 1 x 10 20 cm -3 should be use in order to achieve total volume depletion [16]. The IOFF may be increases when the channel length in the NWJLFET due to the improved gain of the parasitic bipolar junction transistor (BJT) when the base width reduced [19,20]. The parasitic BJT action causes the IOFF to increased, hence ION/IOFF ratio decreases [21]. In this paper, JLNWFET device and the inversion mode FETs of the same device parameters was designed and their performances were compared and analyzed. JLNWFET device of different dielectric materials (low-k and high-k) was also designed and their electrical characteristics were compared and analyzed. The electrical properties such as threshold voltage (Vth), on-off current ratio (ION/IOFF), subthreshold swing (SS), and drain induced barrier lowering (DIBL) were extracted from the I-V curves. Finally, their overall electrical characteristics were compared and validated with the literature review.

RESEARCH METHOD
The simulation was carried out using Sentaurus TCAD software. The device structure was simulated by using SDE Tool and I-V curve was extracted by using Sdevice Tool. Lombardi mobility model and Philips unified mobility model were embedded to consider field-and doping-dependent mobility degradation. Shockley-Read-Hall (SRH) is the dominant generation and recombination process in silicon and other indirect energy band gap materials. It can also dominate in direct band gap materials under conditions of very low carrier densities or very low level injection. Auger recombination model and Fermi-Dirac statistics were also used. The LG of the devices was varied between 7 -120nm and dNW was varied from 6 -10 nm were designed and simulated. SiO2 and high-k dielectric materials such as HfO2 and Si3N4 devices of different LG and dNW were also designed and simulated to obtained electrical characteristics. High-k dielectric was used in the JLNWFET device structure to optimize the electrical characteristics and reduce the SCEs. The electrical characteristics such as VTH, ON-state current, OFF-state current, DIBL, SS and the ON-state to OFF-state current ratio of the devices were analyzed. The parameters and dimension of the device are shown in Table 1 for both the JLNWFET and Inversion-Mode device. The table shows the dimensions of the parameters used in designing the two devices of different LG and dNW. The device parameters of JLNWFET is the same with that of [22] for further validation. Both devices JLNWFET and Inversion-Mode NWFET are fixed to have same device parameters.  The 3D and horizontal cross-sectional diagram of JLNWFET and the inversion-mode device was shown in Figure 1. It shows that JLNWFET has uniform ND from source to drain while the inversion-mode device, channel doping is different to the doping in the source and drain junctions.

RESULTS AND DISCUSSION
The result of the research was obtained and dicussed in three forms:

Impact of variation of LG on electrical characteristics of JLNWFET and Inversion mode FET
JLNWFET and the inversion-mode devices were simulated at both linear and saturation regions which are VDS of 0.05 V and 1 V respectively. The N + region is heavily doped with concentration of 1 x 10 19 cm -3 in order to get high ON-state current to flow between the source and the drain. A small cross section of the channel was used to ensure full depletion of the heavily doped channel resulting in low leakage current as shown in Figure 2. However, when Lg decreases, the leakage current increases. This is due to the short channel effects. Figure 2 shows the I-V curve of JLNWFET of for different LG. It was found that the device with LG = 120 nm has minimum IOFF while the device with smaller gate length, LG = 7 nm has higher IOFF. This prove that as the IOFF decreases with an increase of LG. Figure 2 shows that JLNWFET with LG = 7 nm has lower VTH while device with LG = 120 nm has higher VTH. This shows that as the LG increases, the VTH also increases and vice versa. Figure 3 shows theSubthreshold slope and DIBL with LG variation for both devices. Subthreshold slope and DIBL in JLNWFET shows great improvement than the inversion-mode device as shown in Figure  3. Both the SS and DIBL were limited to 69.98 mV/dec and 54.73 mV/V respectively for LG of 7 nm, compared to the inversion-mode device which has 90.13 mV/dec and 112.15 mV/V respectively for the same LG. However, as the gate length LG increases with constant dNW, the SS and DIBL reduced to the minimum level. For LG of 120 nm, the SS and DIBL of JLNWFET device are 47.77 mV/dec and 69.98 mV/V respectively. Our aim is not only to minimize SCEs but also to improve the scaling in order to obtain the most optimum device structures with optimized electrical characteristics. High doping concentration, ND and small nanowire cross sectional area increases the ON-state current in nanowire junctionless transistor [23]. Metal gate work function and small cross-section area of the nanowire are to ensure full depletion of the heavily doped channel resulting in low leakage current [24]. Figure 4 shows JLNWFET and the Inversion-mode FET demonstrates almost equal ON-state current. For device with LG of 7 nm, JLNWFET and the inversion-mode FET have ION of 3.77 x 10 -6 A and 1.23 x 10 -5 A respectively. However, as the LG increases the ION decreases. The OFF-state shows significant improvement in JLNWFET over the inversion-mode for gate length less or equal to 10nm. For LG of 7 nm, IOFF is 8.68 x 10 -14 A and 2.50 x 10 -12 A for NW JLFET and inversion-mode device respectively. As the LG increases, the IOFF of both devices improves further. JLNWFET has better ION/IOFF ratio for LG below 10 nm. For LG of 7 nm, JLNWFET and inversionmode have ION/IOFF ratio of 4.34 x 10 7 and 4.92 x 10 6 .
The results obtained were tabulated and compared as in the Table 2 for both JLNWFET and the inversion-mode devices.

Impact of variation of dNW on electrical characteristics of JLNWFET and Inversion mode FET
JLNWFET and the inversion-mode devices were simulated using different dNW of 6, 8, and 10 nm using a constant LG of VD of 1 V. For dNW of 6 nm, JLNWFET and inversion-mode has VTH of 0.454 V and 0.443 V respectively. However, as the diameter increases, the threshold voltage decreases for both the two devices because, the VTH depends on the doping concentration, gate oxide thickness, nanowire width and silicon thickness film [25]. The DIBL and the SS shows significant improvement in JLNWFET than in the inversion-mode device as shown in Figure 5. For dNW of 6 nm, the SS and DIBL of JLNWFET and inversion mode are 69.98 mV/dec and 54.74 mV/V respectively as against the inversion-mode FET of 90.13 mV/dec and 112.15 mV/V respectively. Nevertheless, as the dNW increases both the SS and DIBL increases further  Small dNW and high doping and concentration reduce the series resistance for the flow of current in nanowire, hence increasing the ON-state current of the junctioless transistor [16]. Metal gate material was used in order to reduce the gate resistance. Small cross section of the channel allows the gate to deplete the heavily doped channel entirely and obtain a very low leakage current (IOFF) [9]. Figure 6 shows the JLNWFET exhibits higher ON-state to OFF-state current ratio than the inversion-mode device. For dNW of 6nm, ION/IOFF of JLNWFET and inversion-mode were found to be 4.34 x 10 7 and 4.92 x 10 6 respectively. Nevertheless, as the dNW increases the ION/IOFF of both the two devices decreases. This proves that, high doping concentration and small cross-sectional area of nanowire improve the performance of the device. The results of the variation of nanowire diameter (dNW) for LG of 7 nm of both JLNWFET and the inversion-mode devices were obtained and tabulated in Table 3.

Effects of different dielectric materials of the electrical characteristic of JLNWFET
`To optimize the device, JLNWFETs was designed and simulated with different dielectric materials; HfO2, Si3N4 and SiO2 of different LG as in [26]. The remaining parameters and dimensions are the same as in Table 1. The electrical characteristics of the devices was obtained using Sdevice of Sentaurus TCAD, analyzed and compared.  Junctionless transistors are expected to have a very low DIBL and SS effects due to the absent of junction. When LG is small, high-k dielectrics can help to minimize this DIBL effect very effectively. The theoretical limit of SS is 60 mV/decade [26]. In Figure 8, it was found out that HfO2 exhibits better SS and DIBL among the three gate oxides. For LG of 10nm, the SS and DIBL of HfO2, SiO2 and Si3N4 are 64.70 mV/dec and 22.74 mV/V, 74.92 mV/dec and 79.68 mV/V and 68.49 mV/dec and 46.95 mV/V respectively. JLNWFET demonstrates lower IOFF when the LG is large. For LG of 50 nm, the IOFF of SiO2, HfO2 and Si3N4 are 3.81 x 10 -15 A, 1.14 x 10 -16 A and 4.92 x 10 -16 A respectively. For device with LG 7 nm, the OFF-state currents are high i.e. 1.84 x 10 -9 A, 2.66 x 10 -13 A and 1.76 x 10 -11 A for SiO2, HfO2 and Si3N4 respectively. HfO2 reveals better OFF-state current than the other two dielectric materials.  Table 4 for the devices with three different dielectric materials.  The highlighted result (in red box) in Table 4 shows the electrical characteristics of HfO2. It was found out that HfO2 exhibits significant characteristics than SiO2 and Si3N4. It can be observed that for LG of 7 nm, HfO2 has achieved ION/IOFF of 10 7 compared to SiO2 and Si3N4 of 10 3 and 10 5 respectively. SS and DIBL were highly improved to 64.70 mV/dec. and 22.74 mV/V respectively for LG of 7nm in HfO2 than the other two materials. This shows that the proposed JLNWFET with HfO2 is the optimum alternative to improve the scaling and the performance of the device as well as to suppress the SCEs.The electrical properties of this proposed work was compared with the other works in [4,8,11] for LG of 7 nm and 20 nm as in Table 5. For the case of 7nm gate length, it was observed that SS of this proposed work is improved by 20% with 54.7 mV/dec as compared to 68.5 mV/dec. ION/IOFF is also improved by tenfold as compared to [4]. For the case of 20 nm gate length, it was observed that but the DIBL is greatly improved by about 39% with 18.21 mV/V as compared to [8] which is 30 mV/V. Moreover, for the case of 20 nm gate length, it was observed that SS, DIBL and ION/IOFF are greatly improved if compared to [11].

CONCLUSION
JLNWFET and inversion-mode devices have been successfully designed for different gate lengths and nanowire diameters. The electrical characteristics of the two devices was compared and analyzed. The electrical characteristics and performance of JLNWFET of three different dielectric materials (low-k and highk) have been investigated, compared and analyzed. This work discovered that JLNWFET exhibits significant improvement in electrical characteristics than the inversion-mode device especially for gate length less or equal to 10 nm. SCEs such as DIBL and SS are considerably reduced in JLNWFET devices. Although, the JLNWFET with long LG demonstrated higher ION/IOFF and the most optimum SCEs. Our aim is not only to improve performance and SCEs, but also to get the most optimum device's physical parameter. For the same LG and dNW, JLNWFET proved to have better electrical characteristics than the inversion-mode device. JLNWFET with HfO2dielectric demonstrated better SCEs and excellent electrical characteristics than JLNWFET with Si3N4 and SiO2 dielectrics for LG shorter than 35 nm. JLNWFET with Si3N4 exhibits better electrical characteristics and SCEs than HfO2 and SiO2 for gate length longer than 35 nm. To achieve better performance, JLNWFET of LG 10 nm or below is highly recommended. Heavily doped concentration and small nanowire diameter (dNW) of 10 nm or below produced higher ON-state current. Metal gate material was used to reduce gate resistance. To achieve volume depletion, the cross-sectional area of the channel must be small enough in order to deplete the highly doped channel entirely. In both the JLNWFET and the inversion-mode devices, as the ON-state current increases, the OFF-state current also increases which leads to small improvement in the ION/IOFF ratio.