Performance Analysis of Montgomery Multiplier using 32nmCNFET technology

Received Sep 30, 2019 Revised Oct 18, 2019 Accepted Jan 02, 2020 VLSI design vacillating the parameters results in variation of critical factors like area, power and delay. The dominant sources of power dissipation in digital systems are the digital multipliers. A digital multiplier plays a major role in a mixture of arithmetic operations in digital signal processing applications hinge on add and shift algorithms. In order to accomplish high execution speed, parallel array multipliers are comprehensively put into application. The crucial drawback of these multipliers is that it exhausts more power than any other multiplier architectures. Montgomery Multiplication is the popularly used algorithm as it is the most efficient technique to perform arithmetic based calculations. A high-speed multiplier is greatly coveted for its extraordinary leverage. The primary blocks of a multiplier are basically comprised of adders. Thus, in order to attain a significant reduction in power consumption at the chip level the power utilization in adders can be decreased. To obtain desired results in performance parameters of the multiplier an efficient and dynamic adder is proposed and incorporated in the Montgomery multiplier. The Carbon Nanotube field effect transistor (CNTFET) is a promising new device that may supersede some of the fundamental limitations of a silicon based MOSFET. The architecture has been designed in 130nm and 32nm CMOS and CNTFET technology in Synopsys HSpice. The analysed parameters that are considered in determining the performance are power delay product, power and delay and comparison is made with both the technologies.The simulation results of this paper affirmed the CNTFET based Montgomery multiplier improved powerconsumption by 76.47%,speed by 72.67% and overall energy by 67.76% as compared to MOSFET-based Montgomery multiplier. Keyword:


INTRODUCTION
In VLSI design, any modification in the architecture may bring changes in major factors like power, area and speed. A multiplier has a major role in a mixture of arithmetic operations in digital processing applications.The increase in operating frequency, semiconductor technology and chip density has resulted in increased use of power in VLSI circuits, which has become a major problem. A fast growing technology put forth demands for high-speed and efficient real time digital applications [1]. Silicon based technology might probably get reduced by 2020 as the length of the channel in a MOSFET can be less than 10nm. As the silicon based devices face the scaling disadvantage the semiconductor industry is in search for devices and materials [2] that can be incorporated into the contemporary silicon-based technology in the future for a long term [3]. The count of analysing substitute results is single-electron tunnelling, rapid single-flux quantum logic, quantum cellular automata and Carbon Nanotube (CNT). After several experimental analyses, Carbon Nanotube has been found as the most promising alternate material.The diameter of CNT is found to be between 1 to 3 nm and its length extending to a few microns. CNTFETs can be used to a high extent for building both highstrength interconnections and low resistance [4].CNTs can be exploited to build both low-resistance, highstrength interconnections and highly scalable low-power carbon Nanotube field-effect transistors (CNTFET) and single electron tunnelling transistors are one of the basic ideas to replace the silicon MOSFETs with CNTFETs to overcome all the demerits of silicon MOSFETs. The highly scalable low-power Carbon Nanotube field-effect transistors (CNTFET) and single electron tunnelling transistors are quite few among the primary ideas to take over the MOSFETs (Silicon based) with CNTFET in order to surmount the constraints of the former. With the circuit design established on aforementioned devices will require the accessible device models and must be adaptable to the current flow of designs.
The paper is systematized as: In section II the geometrical structure of the carbonanotube field effect transistor (CNTFET) is briefly presented. Section III depicts Proposed Full adder cell and Montgomery Multiplier, Section IV illustrates Performance Analsyis by comparing both MOSFET and CNTFET technology, Conclusion and possible future oversight are inspected in section V.

CARBON NANO TUBE FIELD EFFECT TRANSISTOR
The term CNTFET is abbreviated as Carbon Nanotube Field Effect Transistor and it cites to a FET that resorts to single walled Carbon Nanotube or an assortment of carbon nanotube as the material used for channel instead of the silicon that has been used in the typical structure of MOSFET. During 1998, it was first manifested, that there are major developments in CNTFETs that vow to replace silicon in future electronics as an alternative material. Three presumptions are highly essential to presume that a CNTFET is prevailing in the region of ballistic. Carrier scattering events is quasi-suppressed in the intrinsic channel or channel carriers are scatter-free and all carriers propagating to the drain reach the drain without scattering back to the source. In this case, the carrier's transport is ballistic and in the ohmic zone, the drain current is expressed without depending on the carrier mobility with elementary parameters. This current is proportional to the channel width or nanotube diameter depending on the channel length [5]. The bread of Carbon Nanotube is characterized by capacitors of four different types, namelydrain,source, substrate and gate. The capacitance at gate terminal is reasonably higher than the three others (particularly when using high-k gate dielectrics) capacitors. The total capacitance apexes the quantum capacitance. CNTFETs functions in quantum capacitance limit. The charge at the inception of the channel is almost autonomous of the drain voltage when the gate capacitance is greater than quantum. Semiconducting CNTs were used to fabricate CNTFETs that show promise over silicon based MOSFETs due to their superior electrical characteristics [6] [7].
When a gate capacitance is greater than the quantum capacitance, the charge at the beginning of the channel decreases when drain capacitance increases. The Figure 1 depicts the typical CNTFET device [6]. The 2D electrostatics, parasitic resistance and scattering is the scaling limits of CNTFET which curbs its practical applications.  The device model specification shown in Table 1 represents the model parameters of CNTFET. Primarily, the MOSFET logic circuits are constructed based on a generic Process Design Kit using 32nm Predictive Technology Model (PTM) with 32nm as Physical Channel Length, 1.5nm as thickness of high-k top gate dielectric material (Tox) and 0.35eV as Fermi level of the doped S/D (Efo). Then, the CNTFET PTM circuit models as shown in Table 1 [6] that consist of device modelling implemented in HSPICE circuit simulator [7] are being compared to the MOSFET designs.

PROPOSED METHODOLOGY 3.1. Proposed Low Power Adder
In the field of electronics, pass transistor logic (PTL) Rrefers to various logic families used in integrated circuit design. It curtails the tally of transistors used to compose disparate logic gates by knocking out transistors that are redundant. A full adder is proposed by modifying the existing transistor function full adder as shown in Figure 2. The adder has been restructured and reorganised by removing one PMOS transistor and NMOS transistor along with one inverter. This reduces the overall area, switching activities and power consumption in which the design becomes prominent for low-power applications.A major drawback of PTL is that when the data '0' is passed through the NMOS transistor, it is accurately received at the output and when a 5V voltage is applied to the NMOS pass transistor as data input, the output received is 5V-Vth, vice versa for PMOS.

Montgomery Multiplier
Montgomery modular multiplication has found its use in major digital signal processing applications and cryptographic algorithms. The main aim of the Montgomery multiplier is to reduce the delay and enhance the security of cryptographic algorithms along with the increased speed[9] [10]. The high-speed Montgomery modular multiplication algorithms and hardware architectures use the carry-save addition to prevent carry propagation at each addition operation in the add-shift loop to augment the speed, but the disadvantage is that it requires extra clock cycles which in turn make the complex hardware. The heart of the data security systems is RSA and ECC (Elliptical Curve Cryptography). However, nowadays NTRU is the most widely used algorithms in various cryptosystem play a major role in network security [11] [12].Montgomery put forth an algorithm that performs the modular multiplication without conducting any trial division but still generates some residue. An exponentiation operation that intensively performs modular multiplication is referred to as modular exponentiation. The Modular multiplier gives the definite value of AxB mod M [13]. The Modular multiplier employs a 4*1 multiplexer (MUX4) and Shift Register. The shift register contains the result of first computation. The result of first computation is used to get the final output as shown in figure 3. Therefore, the Modular multiplier performs all the controls needed for the Montgomery multiplier by simply loading the register [14]. The RSA cryptography system requires more number of modular multiplication. Montgomery multiplication is the most dynamic method is used for commutable multiplication. This method is applied to augment the encryption and decryption process [15]. The traditional way of implementing cryptosystems is application specified integrated circuit (ASIC) configuration, whereas the modern method is field programmable gate arrays (FPGA). When comparing both the methods, the latter technique proves to be highly secure and flexible [16]. Montgomery multipliers have evolved over the past few years in order to increase the speed and efficiency of several digital systems. Montgomery multiplication-based multiplier provides high throughput rate when implemented with smaller area and increased speed. This multiplier can be used in RSA cryptosystem and Elliptic Curve Cryptography as it upgrades the security as well as reduce the time consumption [17].  Tables 2 and 3 hold the performance analysis of both existing and proposed Montgomery multiplier 130nm and32nm CMOS and CNTFET technology. From the performance analysis the proposed low power adder and Montgomery multiplier work efficiently than the existing architecture. By the method of restructuring and recombination of circuit design, the proposed adder and multiplier maintains its benchmark with respect to high speed and low power. As shown in table the results depict the efficiency of proposed work in terms of power, speed and energy when compared to existing designs. The 32nm channel CNT can deliver output current comparable to those of the MOSFET. This is conceivable by preserving the ballistic transport over distances and the superior current density of a single CNT creating the channel. It can also be inferred that the power, delay and PDP obtained in proposed architecture of both proposed low power adder and Montgomery multiplier, the performance is much better in CNTFET technology.

CONCLUSION
Montgomery multiplier is thus designed in both CMOS 130nm and 32nm as well as 32nm CNTFET technology and the performance specifications like average power, delay and the power delay product are analysed and distinguished.The operating voltage for the 130nm CMOS is 3.3V and 32nm CMOS is 1V and that of the CNTFET is 1V. All the designs are said to work at the operating frequency of 1GHz. From several analyses it has been proved that the 32nm CNTFET adder design devours fewer power when compared to 32nm CMOS circuit design. The 32nm CNTFET Montgomery multiplier circuit consumes less power when compared to 32nm CMOS design. The proposed 32nm CNTFET Montgomery Multiplier consumes 74% less power when compared to 32nm CMOS design.CNTFET is the assuring device for the future electronics as it attains the greater performance on the grounds of power, delay and power delay product. CNTFET devices are basically less prone to failure and are highly reliable.The future circuits designed with CNTFET will be a prominent one.