Design Analysis and Development of Inverter Topologies for Industries

Received Jan 9, 2018 Revised Jan 21, 2018 Accepted Feb 11, 2018 This paper presents the most common inverter topologies and its design, analysis and development schemes. The main objective is to design and compare the three topologies of multilevel inverter for industries. These three topologies are mostly effectively and efficiently for quality improvement of the output voltage waveform of inverter. Photovoltaic (PV) and wind power generation (WPG) i.e. the renewable energy systems are playing a vital role in energy production. But, solar photovoltaic power (PV) has the prospective to develop one of the foremost suppliers to the future electricity supply. Therefore, Low voltage solar PV systems need a high voltage expansion converter for units of grid connection with multilevel inverter. The multilevel inverter topologies are being used in applications of medium and high power such as an active power filter, FACTS devices and a machine current due to their various merits in terms of power supplies low power dissipation, low harmonic distortion in voltage output waveform. Therefore, the simulation of multilevel inverter topologies is done and finalized that cascade multilevel inverter topology is more suitable as compared to other two by using MATLAB/SIMULINK. Keyword:


INTRODUCTION
In modern years, many applications of industries have initiated to require medium or high power for their task [1].But, it is very difficult for a grid medium voltage to associate directly a single power rating of semiconductor switch.A multilevel power inverter arrangement has been presented since 1975 for example an alternative in high power and medium voltage situations and the arrangement of switching angles are very important.Multilevel inverter goes up to high switching voltage using a sequence of step voltages, each of which is depend on the power devices rating individually.For multilevel inverter, some topologies are classified in two groups depending on the number of independent dc source.In recent years, the greatest corporate topologies are diode-clamped/neutral-point inverter (NPC), flying capacitor/capacitor-clamped (FC) inverter and cascade H-bridge (CHB) inverter.The topology of NPC is some way similar to the FC with difference that flying capacitors are replaced by clamping diodes.CHBs inverters are classified by series connection of two or more single-phase H-bridge inverters.Fundamental switching frequency and high switching frequency PWM methods are used to operate the multilevel inverters by means of efficiency high and switching losses low.In the CHB multilevel inverter (MLI), a separate DC voltage source is required for each level and a PV cell or battery is to be connected for each DC source.

DIODE CLAMPED MULTILEVEL INVERTER
A 3-level diode-clamped inverter correspondingly so-called the neutral clamped inverter presented by Nabae, Takahashi and Akagi popular 1981 [1].Some research scholars published articles that have conveyed outcomes up to 4, 5 and 6-level diode clamped inverters.After reading [1]- [5], we conclude that for a 1-Ф three-level neutral clamped inverter at any given time a set of 2 switches is ON.This type of inverter is suitable on an AC transmission line for transmission of DC current or variable speed motors.
In Figure 1, the output voltage in DC is separated in series form of two bulk capacitors C 1 and C 2 into 3 levels.The two diodes D 1 and D 1 ' hold the switch voltage to the DC-bus voltage of half level.And, when we turn ON the switches S 1 and S 2 , the the terminals voltage across a and 0 is V dc , i.e., V ao = V dc .Note the output voltage Vao is DC and Van is AC.The voltage difference between voltage V an and V ao is the voltage across the capacitor C 2 , which is V dc /2 as in Table 1.In Figure 2, a 3-Ф 7-level diode-clamped inverter is given and a common voltage DC bus is joint by each of the 3-Ф which is subdivided by 6 capacitors into 7-level [6].The output possible voltage levels for each inverter phase with reference to zero i.e. voltage V 0 is shown in table 2 [6].When the switch of semiconductor device is ON, the state condition is one (1) and when the switch of semiconductor device is OFF, the state condition is zero (0).It has 6 corresponding switch pairs in each phase so that turning ON one of the switches of the pair require that its other corresponding switch is to be turned off.The corresponding switch pairs for phase leg 'a' are (S a1 , S a'1 ), (S a2 , S a'2 ), (S a3 , S a'3 ), (S a4 , S a'4 ), (S a5 , S a'5 ) and (S a6 , S a'6 ).The line voltages V ab , V bc and V ca involves of a phase a-b, b-c and c-a voltages respectively.When the lower switches all S a'1 through S a'6 are turned ON, D 5 must block 5 voltage levels or 5V dc as per table 2 for phase 'a'.Similarly, D 4 must block 4V dc , D 3 must block 3V dc , D 2 must block 2V dc and D 1 must block V dc .If we designed this inverter, each blocking diode has the same voltage rating; D n will need 'n' diodes in series.

FLYING CAPACITORS MULTILEVEL INVERTER
In 1992, Meynard and Foch presented a flying capacitor (capacitor clamped) typed inverter [1].This inverter circuit is just like a diode-clamped inverter.The design needs single 2 switch combinations to generate an output voltage waveform.

Figure 3. 3-level type capacitor-clamped inverter
The inverter offers a 3-level output voltage waveform across terminals a and n, i.e., V an = V dc /2, 0, or -V dc /2 as shown in figure 3.For voltage level V dc /2, switches S 1 and S2 requisite to be turned ON; for voltage level -V dc /2, switches S 1 ' and S 2 ' requisite to be turned ON; and for voltage level 0, either pair (S 1 ,S 1' ) or (S 2 ,S 2' ) desires to be turned ON.In figure 4, a 3-Ф 7-level capacitor-clamped inverter is given (similar of figure 2) [6].

CASCADED H-BRIDGE MULTILEVEL INVERTER
In 1995, Manjrekar introduced a cascade H-bridge typed inverter [1].In this paper, a cascade multilevel inverter in each phase requires 's' DC sources for (2s+1) level.For the interest purpose we can use e. g. battery, fuel cell of a DC power source [7].A 3-Ф building block of a 13-level cascade multilevel  5 as per the table 3 configuration for each Hbridge inverter.The topology of multilevel inverter has the minimum components as compared to other topologies for a specified number of levels.The Cascaded 13-level inverter necessitates 6 separate DC sources per phase leg; this means that 6, H-bridge inverters are used for 1-Ф structure.Each 1-Ф, 13-levels CMI is connected as star it means that one of the terminals is connected at common point and the other terminal is connected to a 3-Ф series load [7].

Figure 5. 3-Ф, 13-level cascaded h-bridge inverter
The output phase voltage is synthesized by the addition of outputs of individual inverter, for example, the phase voltage of 'a' in 13-level is:

COMPARISON OF DIFFERENT TOPOLOGIES IN MULTILEVEL INVERTER
As compare to other two, cascade multilevel circuitry is simple because it doesn't have extra auxiliary capacitors and diodes.And, we can be found the level of the voltage on each stage, number of output level and number of switches values by formulas which is used in these topologies as shown in table 4.There are many types of modulation control methods that we have used to control it i.e. selective harmonic elimination or harmonic optimization (SHEM), space vector PWM, sinusoidal pulse width modulation (SPWM) and active harmonic elimination.But, SHEM technique is simple, show less harmonic and efficient output voltage waveform and it completely depends on the no. of levels information.The selective harmonic elimination method is more appropriate for a multilevel inverter circuit and low Total Harmonic Distortion (THD) output voltage waveform is possible without any filter circuit for using this technique.57 Where : Vn = amplitude of voltage harmonic of nth order, Vdc = DC voltage s = number of the bridges in each phase n = odd harmonic order

EXPERIMENTAL WORK
The figure 6 and 9 give the voltage difference between voltage V an (AC output) and V ao (DC output) is the voltage across the capacitor C 2 , which is V dc /2 (V dc =100V) as shown in figure 7, 8 and figure 10, 11 respectively.But in figure 12 with fewer components as compared to other two topologies, output AC voltage is V dc as shown in figure 13.Analyzing these results indicates that the cascade structure has less total number of elements comparable to the other topologies.Instead, it displayed a higher number of power sources, which can be taken as an advantage leading to limit the stress on the switches and decrease the THD.

CONCLUSION
The ceremonial of the art of multilevel power inverter technology for different three topologies is demonstrated in this paper.Therefore, after designing these topologies we established that cascade H-Bridge inverter is superior to others while we compare the modulation structure, reliability and switching methods with other two topologies.For manipulative the required output voltage level on each step in each topology, a procedure has been clearly defined and the required number of switches also increased as the number of levels in the conventional methods is increased.Finally, Matlab/Simulink based model for 3-level of these three topologies and cascaded 13-level inverter is developed and simulation results are presented.

Table 3 :
Switching Pattern for H-bridge Inverters

Table 4 :
Comparison of Topologies in Multilevel Inverter and Corresponding Equipment which are used in Circuit