Design and Evaluation of the Efficiency of Channel Coding LDPC Codes for 5G Information Technology

This paper proposes a result of an investigation of a topical problem and the development of models for efficient coding in information networks based on codes with a low density of parity check. The main advantage of the technique is the presented recommendations for choosing a signal-code construction is carried out taking into account the code rate and the number of iterations decoding for envisaging the defined noise immunity indices. The noise immunity of signal-code constructions based on low-density codes has been increased by combining them with multi position digital modulation. This solution eventually allowed to develop a strategy for decoder designing of such codes and to optimize the code structure for a specific information network. To test the effectiveness of the proposed method, MATLAB simulations are carried out under for various Information channels binary symmetric channel (BSC), a channel with additive white Gaussian noise (AWGN), binary asymmetric channel (BAC), asymmetric channel Z type. In addition, different code rates were used during the experiment. The study of signal-code constructions with differential modulation is presented. The efficiency of different decoding algorithms is investigated. The advantage of the obtained results over the known ones consists in determining the maximum noise immunity for the proposed codes. The energy gain was on the order of 6 dB, and an increase in the number of decoding iterations from 3 to 10 leads to a gain in coding energy of 5 dB. Envisaged that the results obtained can be very useful in the development of practical coding schemes in 5G networks.


INTRODUCTION
In information networks and mobile communication networks, the data transmission is used between user-assigned equipment and base stations. Accepted data differs from transmitted one through errors caused by noise, obstacles and fading. To fix these cellular networks errors use forward error correction codes.
Thus, an important process that accompanies the operation of modern information networks is noise immunity coding [1][2][3][4][5][6]. High requirements for the quality of digital information transmitted in the telecommunication network is provided by the correction of errors that accompany the transmission process. The task is to find and study the optimal in terms of time and computing resources of encoding and decoding devices that play an important role in the design of advanced signal resources. The task of detecting and correcting errors in telecommunication networks is determined by such factors as external noise as well as the presence of interference due to the influence of neighboring base stations transmitters.
Currently, the development of efficient signal code constructions (SCC) for advanced 5G networks lies in the search for the optimal compromise between low power consumption, cost, decoding complexity and

RESEARCH METHOD
In this section, the implementation of error correction in 5G is presented. Considered a block diagram of the channel with LDPC and automatic repeat request. The principle of formation of LDPC codes and analytical model of LDPC description is described.

Implementation of Error Correction in 5G
The main features of the implementation of the error correction process in 5G networks can be set up [1]. Error correction in 5G networks is implemented on the basis of three levels -physical, MAC-layer, the layer negotiates protocol stacks and monitors radio communication (RLC) [2][3].
LDPC codes are linear block codes. They are defined by a check matrix H containing zeros and a relatively small number of units [9]. LDPC codes are characterized by high code rate which led to their choice for use on high-speed traffic channels of 5G networks.
The implementation of mathematical algorithms for calculating the cyclic redundancy code (CRC), channel coding (CC) and rate matching (RM) is implied at the physical level Fig. 1.
If the receiver gets a packet with errors that are not corrected by the channel decoder the receiver stores this packet in the receive buffer and requests retransmission. The transmitter within each retransmission (at the request of the receiver) transmits a data packet containing different code sequences. Each code sequence is created from fixed information bits, but using different templates for deleting (or punching) bits by the rate recovery unit (RR). The used template is determined by the value of the reservation version (RV). The RV value for each retransmission is determined in advance (for synchronous mode) or transmitted in the control information unit (DCI) transmitted on the physical control channel (for asynchronous mode). The transmitter can use different modulation schemes for different requests. After each retransmission, the receiving part forms

Formation of LDPC Codes
The issue of coding gain increasing in the field of low noise remains open when designing 5G networks. The concern is especially relevant for digital television networks, optical communications and data networks. The development of methods and algorithms for the synthesis of LDPC codes by some set of criteria [2,8] is one of the possible ways to solve this problem. Most of the criteria for the formation of check matrixes are based on cycles in Tanner graphs and their relationship which makes it important to quickly identify cycles [12].
The formation of LDPC-code is realized on the basis of the base graph Gr=(ν,c,E) -a two-dimensional undirected multigraph, consisting of a set of symbolic (ν) and test (c) vertices as well as a set of branches (E) that connect vertices with ν and c with each other, Fig. 2.  The general structure of the QC-LDPC base graph contains columns divided into three parts: information columns, main parity columns and extended parity columns. The strings are divided into two parts: kernel check strings and extension check strings. Fig. 3 shows the base matrix consists of five submatrices: A, B, O, C and I. The submatrix A corresponds to the systematic bits. The submatrix B corresponds to the first set of parity bits and has the shape of a square matrix with a two-diagonal structure. The submatrix O is a zero matrix. A single parity check (SPC) extension is used to support HARQ to support lower speeds. The submatrix C corresponds to SPC rows. In Fig. 3 -I-unit matrix which corresponds to the second set of parity bits (SPC extension). The A and B combination is called the nucleus and the other parts (O, C, and I) are called extensions. Fig. 2. The 3rd Generation Partnership Project (3GPP) identifies two rate-compatible base channel coding graphs. The base graphs BG1 and BG2 have similar structures. However, BG1 is designed for longer block lengths (500<K<8448) and higher code rate (1/3<R<8/9). BG2 is designed for shorter block lengths (40<K<2560) and lower code rate (1/5<R <2/3).

Analytical Model of LDPC Description
The description of the characteristics of irregular LDPC-codes ensembles will be carried out using the distribution of degrees. The degrees distribution of LDPC-codes is given by a pair of polynomials: Where the coefficients γi are the fraction of the graph branches associated with the symbolic nodes of degree-i, and βj is the fraction of the graph branches associated with the test nodes of degree-j. In this case, the polynomial β(x) is the distribution of the test node degree, and γ(x) is the distribution of the degree of the symbolic node (shown in Fig. 2).
The code rate is determined by the formula: Where N is the number of symbolic nodes; M is the number of test nodes; l is the number of graph branches.
Quasicyclic QC-LDPC codes were adopted as the channel coding scheme for 5G data networks. LDPC codes are determined by their check matrixes. The test matrix is defined by an array of permutation matrixes. The QC-LDPC code parity check matrix H consists of an array of permutation matrixes and zero matrixes of the same size (shown graphically in Fig. 3).
The permutation matrix is a square matrix (b×b), in which each subsequent row is formed by a cyclic shift to the right of the previous row. The LDPC code is determined by a matrix of n×m size where n is the length of the code and m is the number of test bits in the code.

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5G QC-LDPC codes (quasi-cyclic codes) use reduction and puncture procedures to obtain the desired length of information and adapt the rate to the network [17].
The format of the check matrix as a Tanner matrix (3) and (4) allows to form a method of decoder operation. In this case both the symbolic and test nodes of the Tanner graph can be interpreted as computational elements and the edges of the graph will form a set of connections between the computing elements and the memory cells. They will be used to store the reliability values calculated during decoding.
The matrix H has a mutually unique mapping with the next matrix: Where P is the exponential matrix. Each record in P is formed by a certain shift value. Several lift sizes are recommended for one exponential matrix to adapt different lengths of information.
A parallel update of the bits reliability in the check matrix included in the various tapes is proposed. This structure allows to increase the bandwidth of the decoding scheme and to carry out processing at a speed of the order of Gbit/s (Fig. 5).

RESULTS AND DISCUSSION
In this section, the results of research are explained and a discussion is held. The research results contain a comparison of different types of signal-code consntuction with LDPC. The efficiency of the encoded in different channels was assessed by changing the code rate, changing the number of decoding iterations, changing the shape of the modulating signal, the type of decoding algorithm, with different types of redundancy.

Efficiency of LDPC Codes in Information Networks
Determining the decoding efficiency of the LDPC codes of the receiving part is shown in Fig. 6, taking into account Fig. 5. Block A is implemented by adaptively forming a set of M-PSK channels [28][29][30] taking into account intersymbol interference. The M-PSK unit was designed as a channel-demodulator finite state machine. The main design of the unit is implemented in the form of a shift register at the input of which are the flow rates that form the M-PSK. The length of the register was determined by the memory of the channel with intersymbol interference.
The demodulator calculates the aposterior probability of binary symbols based on network status information. The calculation is performed taking into account the prior probabilities from the Decoder SN block. Decoder SN is associated with symbolic nodes in two-dimensional graph (Fig. 2). The block calculates the probabilities of each binary symbol based on the probability obtained from the Demodulator and the information obtained from block B. The restrictions imposed on a particular SCC are taken into account. Block B contains only part of the decoder -Decoder TN. This block is associated with test nodes in the twodimensional graph of the code (Fig. 2). The SN decoder calculates the probability of each binary character based on the a priori probabilities obtained from the Decoder SN block.
In Fig. 7 and Fig. 8 shows the synthesized block diagram of the LDPC encoder and decoder. The main purpose of the controller unit is to provide a process for managing the information flow of data that follows into the memory unit (Fig. 7). Next, there is a formation of control signals which are guided by the rest of the blocks. The encoder circuit includes a lookup table (LUT) block containing the check matrix construction. The shape of the check matrix for the 5G standard was modeled [2]. The Shifter block is located at the output of the LUT. The parity generator generates the parity bits that are used to calculate the parity bits for the rows of the parity matrix. We also apply a selector block that controls positions in the construction of a parity check matrix. The circuit contains an XOR Unit that provides modulo operation and is thus the last link in the encoding process. In the decoder circuit (Fig. 8), the block is the Functional Processing Unit.
In fig. 9 shows a synthesized hardware description language (HDL) model of an LDPC decoder.

Figure 9. HDL is the LDPC Code Decoder Model for Research
Its purpose is to calculate the messages of the SN and TN by the method of multilevel Belief Propagation of using the Min-sum approximation algorithm [16].
The mathematical model of the decoder circuit can be represented on the basis of a statistical parameter as the message distribution function (MDF). If each m message in the code set has the same and known distribution (p(m|a)), where а is the corresponding bit. MDF can be represented by the formula: Where JS is the block output function of Demodulator M-PSK, JV is the MDF passed to Demodulator (Fig. 6).
The diagram that characterizes the decoder operation is presented in Fig.10. In Fig. 10, the X-axis represents the MDF change at the output of the TN decoder (see Fig. 6), while the Y-axis describes the output of the SN decoder block. This diagram is used here to describe the operation of the decoder in the event of a recursive update. In other words, this interpretation allows you to determine the dynamics of the interaction of the components of the decoder. If the MDF process tends to 1 on the graph, you can get a positive trend in reducing the bit error.The obtained type of decoder characteristics was used to form a strategy for curves changing in Fig.10 by transforming the design features of the LDPC code. Such a strategy is appropriate in the case of decoding convergence while minimizing the number of iterative cycles to ensure the required SNR. The obtained type of decoder characteristics was used to form a strategy for curves changing in Fig.7  A significant number of works on LDPC-coding [6][7][8][9][10][11][12][13][14][15][16] do not fully describe all the potential of pointed codes. Thus, the study of LDPC codes for communication memoryless channels is quite relevant for networks, in particular in the case of trellis code modulation and the formation of trellis structures [14]. Figure 10. Diagram characterizing the decoder operation: 1) memoryless channel; 2) JB -1 ; 3) channel with intersymbol interference Fig. 11 shows a study of the efficiency of LDPC codes for a binary symmetric channel (BSC), a channel with additive white Gaussian noise (AWGN). Binary asymmetric channel (BAC), asymmetric channel Z type were also used. Codes with 1/2, 1/4, 3/4 speeds were used for a codeword with a length of 10000 bits. The decoding process stopped when 50 iterations were reached. Figure 11. Noise immunity schedules for telecommunication channels with LDPC codes and 1/4, 1/2, 3/4 code rates: 1 is AWGN; 2 is Z-BAC; 3 is BSC; С is the capacity (vary from 0 to 1 for binary characters) A code of 12·10 3 length was used. Up to 30 iterations of decoding were used for the circuit with differential encoding and up to 100 iterations were used for the circuit without differential encoding. Fig. 12 and 13 presents the results of the noise immunity study for three modifications of LDPC codes: 1) for LDPC code with a speed of 1/2 while DQPSK; 2) LDPC at a rate of 1/2 which is synthesized for 8DPSK; 3) LDPC at a rate of 3/4 while DQPSK. The SNR values corresponding to the bandwidth limit for a particular SCC are represented by vertical lines. The bandwidth limit (spectral efficiency of 1 bit per channel used) for QPSK and  . 13 shows the results of LDPC-codes and М-PSK for memoryless channel study. The research was conducted for two scripts: use of differential coding and without differential encoding. Figure 13. SCC noise immunity schedules on LDPC-codes basis for memoryless channel: 1 is 8PSK, R=3/4; 1*is 8DPSK, R=3/4; 2 is 8PSK, R=1/2; 2*is 8DPSK, R=1/2; 3 is QPSK, R=1/2; 3* is DQPSK, R=1/2 In general, the result of the study indicates a certain advantage (energy gain) of SCC without differential encoding (DC) compared to the system of differential encoding. In this case, SCC without DC had a gain of up to 1.6 dB. Meanwhile, it should be noted that SCC based on LDPC-codes and memoryless M-PSK have a higher error level than SCC with DC.

Study of Noise Immunity of LDPC Codes
Fig. 14 presents the results of the study of SCC noise immunity based on LDPC codes and the use of different decoding algorithms for the decoder presented in Fig. 6. In particular, the following algorithms were  [17,19]. The performance of each algorithm for the AWGN channel was determined. The Layered Belief Propagation algorithm for the used QC-LDPC code with 16-QAM modulation is 0.15 dB more efficient than the Belief Propagation algorithm and 0.9 dB more efficient than the Offset Min-Sum algorithm according to the energy criterion at BER=10E-5 level. The Normalized Min-Sum algorithm has the lowest energy efficiency. The dependence of bit errors number on the SNR for the LDPC code with different types of modulation is presented in Fig. 15. QPSK modulation [28,29] has the best energy efficiency for AWGN. 16QAM modulation by 6 dB is more energy efficient than 64QAM modulation and has 1.5 times lower spectral efficiency [30]. The concept of using 5G LDPC codes is formed on the support of functional rate negotiation to select any number of transmitted bits. The HARQ (Hybrid Automatic Repeat Request) operation and the corresponding 5G LDPC code matching operation are controlled by the redundancy version (RV) (range 0 to 3). The redundancy version is related to the position of the column of the base graph ( Fig. 2 and Fig. 3). The length of the SCC for each redundancy version is determined by the number of available network resources. Fig. 16 presents the results of a study of the impact of the redundancy version on the performance of LDPC codes.
Increasing LDPC code rate from R=0.25 to R=0.44 requires an increase in transmitter power by 2.5 dB. 5G-LDPC codes with different rates and QPSK modulation (Fig. 17). The lower the code rate is in an

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LDPC-encoded network, the higher the energy efficiency is. The transition from code rate 1/5 to code rate 9/10 for QPSK modulation requires an increase in transmitter power by 4 dB. It is necessary to increase the transmitter power by 10 dB when junction from QPSK modulation to 64QAM modulation with 2/3 code rate. The transition from 1/5 code rate to 9/10 code rate requires the increase in transmitter power by 11 dB to 64QAM modulation. Figure 16. Study of energy efficiency of SCC LDPC+QPSK with different types of redundancy (RV): 1 is RV=0; 2 is RV=2; 3 is RV =3; R=0.44. Figure 17. Noise immunity schedules of SCC LDPC+QPSK and different encoding rate: 1 is 1/5; 2 is 2/3; 3 is 9/10 As the length of the block increases, the energy efficiency of the network increases. As the length of the transport unit increases from A=2000 to A=10000, the energy efficiency increases by 1.5 dB.

CONCLUSION
To ensure high rate and low latency in encoding and decoding schemes, it is important to design them correctly for unstructured LDPC codes. Incorrect design of encoding and decoding schemes can lead to significant losses both on storage of the code structure and on rate of processing schemes. Code development should take into account the specific type of SCC and the modulation method used in the network.
The developed HDL model of LDLC decoder for researches is presented. SCC noise immunity schedules on LDPC codes and different types of digital phase modulation optimized for networks allow assess the impact of differential modulation. The use of pointed modulation reduces short cycles during processing and thus counteracts the saturation of the noise immunity curve. In this case, SCC without DC had a gain of Increasing the number of decoding iterations from 3 to 10 leads to an energy gain of encoding at the level of 5dB (BER=10E-5). In addition, the limit of convergence of network bandwidth with LDPC is determined by the code structure and depends quite indirectly on the type of channel.