Analytical current Model for Dual Material Double Gate Junctionless Transistor

A Transistor model with bulk current is proposed in this article for long channel dual material double gate junctionless transistor. The influence of different device parameters such as body thickness, channel length, oxide thickness, and the doping density on bulk current is investigated. The proposed model is validated and compared with simulated data using Cogenda TCAD. The model is designed by Poisson’s equation and depletion approximation. Current driving capability of MOSFET is improved by dual material gate compare to single material gate.


INTRODUCTION
In 21st century, Silicon on Insulator was known as Integrated Circuit Technology. According to International Technological road map MOSFET channel length should reduce. Short channel effect has problems such as increase in subthreshold swing, decrease in Ion/Ioff ratio, drain induced barrier lowering, and transconductance etc. These short channel effect problems can be overcome by different types of transistors. At the time of formation of source and drain junction while using doping profile, thermal budget poses big challenge. However, junctionless transistor is best candidate for improving short channel effect problem because of very low thermal budget. This was reviewed in the literature [1] [2]. Junctionless transistor is more simple compared to inversion model MOSFET because of junctionless fabrication procedure. Double gate junctionless transistor is best candidate for CMOS technology. However, junctionless transistor suffers from less drain current and transconductance due to high doping concentration in the channel region [3]. The concept related to Dual material gate junctionless transistor is studied in literature [4] [5].
Dual material gate (DMG) junctionless transistor improves transconductance and carrier transport efficiency. Peak electric field at source side accelerates more electrons due to DMG structure due to which current driving capability increases. M.Jagdesh kumar and Anurag Chaudhari designed two dimensional analytical model for channel potential of DMG SOI Transistor in order to improve short channel effect problem [5] [6]. Hougin Lou et. al demonstrated dual material gate junctionless nanowire transistor which showed significant improvement in transconductance, output conductance and cut off frequency in comparison with single material gate junctionless nanowire transistor [7]. Ratul K.Baruah designed analytical model for channel potential of dual material gate junctionless transistor by using high-k spacer. However, because of using high-k spacer cut-off frequency of this MOSFET reduced drastically [8]. Gnani et.al presented a design of analytical drain current model for junctionless ultra thin body silicon on insulator transistor and this model design was used under gradual channel approximations which neglected short channel effects [9]. In a work  [11]. In [12] current model of subthreshold region was not mentioned. Ekta Goel et.al demonstrated analytical model of threshold voltage for graded channel dual material double gate MOSFETs, but drain current model not found in this paper [12]. In junctionless transistor, current flows through bulk of channel region. Jaspreet Singh et.al demonstrates the surface potential model and drain current based on surface potential model [13]. However, channel thickness, oxide thickness and doping density affection on drain current is not found in this paper. Ashutosh Kumar et.al demonstrate surface potential model of a Dual material double gate junctionless FET, however, the drain current model is missing in this article [14]. Balraj Singh et.al demonstrate analytical drain current model in subthreshold region and affection of channel thickness, doping density, channel length on drain current of single material double gate junctionless transistor [15]. Objective of this paper is to demonstrate bulk current model and subthreshold current model of dual material double gate junctionless transistor that are not found in literature.
In this paper, a simple analytical expressions are used to describe bulk current for dual material double gate junctionless transistor in linear and subthreshold region. The model is validated by comparing simulation results of COGENDA TCAD using 2-D structure. Basic drift diffusion model, impact ionization model, Fermi Dirac statistic, band to band tunneling and low field mobility model are incorporated in this simulation software as shown in equation (1). μ0 is low field mobility model.
Authors in [16] demonstrated Zener tunneling in semiconductor using this software. Only default parameter values of different models used for simulation. In the proposed model, the oxide thickness, channel length, doping density and channel thickness are varied to study addition effect of these on drain current.

BULK CURRENT MODEL
In Dual Material Double Gate Junctionless Transistor (DMDGJLT) MOSFET simulation, the following process/device parameters are used as in Table 1. An approximation method is used in the Model for dual material double gate junctionless transistor. Further to solve the Poisson's equation in the channel we followed accumulation mode transistor [17]. To determine the depletion width Xdep in the bulk current regime the following equations are given below. (2) εsi is the permittivity of silicon, Nsi is channel doping density. VG is the gate voltage, VFB is flat band voltage. V(y) is channel potential at y in the channel. In expression Cox=εox/tox, εox is oxide permittivity and max min 0 min 300 1 300 Cdep is half channel depletion capacitance, Cdep=2εsi /tsi Ceq is equivalent capacitance given by series connection Cox and Cdep. In DMDG JLT channel thickness is very thin compared to oxide thickness. Therefore, tends to 1 The bulk current through the channel should satisfy ohm's law, dV=I.dR, where dR is differential channel resistance.
W is channel width, µb is bulk electron mobility, Nsi is channel doping density, q is electron charge, tsi is channel thickness. Using graded channel approximation, ohm's law is integrated with dR1 and dR2 given by (6) and (7). Bulk current under gate1: (10) Bulk current under gate2: μb is electron mobility and W is width of channel and L is channel length, VFB1 and VFB2 is flat band voltage 1 and flat band voltage2, respectively. Threshold voltage equation is VTH1=VG -VFB1-(qNsitsi/2Ceq) and VTH2=VG-VFB2-(qNsitsi/2Ceq). Work function of silicon channel is Wsi=4.05+(0.56-(0.026*log(Nd/Ni))).When VDS is equal to VGS-VTH then MOSFET is in saturation state. When more drain voltage is applied then pinchoff point move towards source side. In saturation region drain to source voltage square term is negligible. Flat band voltage is different for L1 and L2, hence workfunction is different under gate1 and gate2. Channel potential distribution in the channel is solved using one dimensional Poisson equation [18]. (12) ϕ(x) is potential at silicon silicon interface, ϕs is surface potential, tsi is channel thickness, εsi is dielectric constant of silicon. Nsi is doping density of channel. The area of electon concentration near the source is (13) Electron concentration is an exponential function of ϕ(x), the electron concentration contributes mainly N(0) at xmin. The position xmin at which a potential is minimum.
We find that xmin=tsi/2. Substituting xmin=tsi/2 into (11) results in: Subtracting (5) into (6), we have (17) Assuming that the change in potential corresponding to conductive channel is in (13), developing exponential term in taylor series at ϕmin and taking first order term (18) (19) n1 is electron concentration under gate1 and n2 electron concentration under gate2. When the channel is fully depleted, ϕs can be obtained as Thus the subthreshold current due to gate1 (20) Subthreshold current due to gate2 (21) dn is diffusion coefficient dn=µn x (KT/q), (KT/q=0.026V). VT=KT/q is thermal voltage. W is width of channel and its value is 1μm. Channel length of gate1 is L1 and gate2 is L2.   Figure 1 shows that drain current versus drain to source voltage changes from -0.4V, -0.1V, 0.1V and 0.4V and VDS varies from 0 to 1V. Here, parameters are, channel length 0.1μm, tox=7nm, channel thickness 10nm and doping density 1x10 19 per cm -3 . As shown in above graph, model calculation (line) match (agrees) with numerical simulation (symbols) for different gate voltages. As like conventional MOSFET, VDS is equal or greater than VGS-VTH in such a case (then) MOSFET works as saturation region. In this diagram, it is observed that current saturates due to velocity saturation of shorter channel length. Because of dual material gate, current driving capability of MOSFET increases in comparison with single material gate MOSFET [7] [19]. When gate voltage is 0.4V, and VDS=1V then current is 5.9x10 -4 A. When current increases then transconductance of MOSFET increases and this benefit for analog circuit.  Figure 2 shows that drain current versus gate voltage for different channel length. When channel length increases threshold voltage of MOSFET decreases. It has been observed that off state current decreases when channel length increases. Off state current is 10 -8 A, 10 -11 A and 10 -11 A at channel length 100nm, 110nm and 120nm respectively at VGS=-1V. In junctionless transistor more barrier between source and channel at channel length increases, hence off current decreases. It has been observed that subthreshold slope (SS=dVG/d(log(ID)) remains constant for all channel length shown in Table 2. It means that short channel effect problem also improved due to dual material gate junctionless transistor. It is observed that there is a good correlation between simulation and model result.  Figure 3 shows that drain current versus gate voltage for different doping density. When doping density decreases then threshold voltage of MOSFET increases and current driving capability increases due to carrier mobilty increase as well as due to reduction of ionization scattering in the channel [20]. It is observed that less doping density is used then off current decreases. It has been observed that current driving capability increases when doping density increases which means less ionization scattering effect on mobility and already very less surface roughness mobility degradation in junctionless transistor because of current flowing through bulk. When channel is lightley doped, number of carriers availability for conduction is very less and hence channel is completely depleted and higher voltage required to diminish the depletion for current conduction. Finally it observed that there is a good corelation between model and simulation.  Figure 4 shows that drain current versus gate volatge. Threshold voltage of MOSFET decreases when thickness of sio2 layer increases. Dual material double gate junctionless transistor improves the performance when subthrehold slope decreases, DIBL value decreases and ION/IOFF ratio increaes. Effect of oxide thickness variation on threshold voltage is maximum in comparison with channel thickness and doping density. When VGS is 0V and when tox=3nm then MOSFET is easily in the off state when compared to 7 and 5nm oxide thickness MOSFET. It has been observed that when gate oxide thickness increases then it has less effect of gate voltage on depletion width of channel. Smaller oxide thickness means bigger gate capacitance that is more capable of depleting the channel and producing small OFF current. Figure 5 shows that variation of drain current versus gate voltage for different channel thickness. When channel thickness increases then threshold voltage decreases. Subthreshold slope (SS=dVG/d(log(ID)) is 90 mV/decade for channel thickness 6nm and 80 mV/decade when channel thickness is 8 and 10nm. In camparison silicon film thickness 6nm, the silicon film thickness 10nm will enhanced ON current by approximately 2 orders of magnitude. On the other hand decreases channel thickness increases the resistance,  If Channel thickness and gate oxide of DMDGJLT decreases then subthreshold slope decreases which means that off current decreases. It has been observed that gate oxide thickness of junctionless transistor increases then control of gate on channel decreases. No full depletion in channel when maximum gate oxide thickness of junctionless transistor, which is off current increase. Table 2 shows that SS value at different doping density at tsi=10nm, tox=3nm, L=100nm and SS value at different channel length at tsi=10nm, tox=3nm and ND=9x10 18 cm -3 . Moreover, DIBL value for gate oxide thickness 3nm and another parameter remains constant, while DIBL=VTH(VDS=0.05V) -VTH(VDS=1V) = 30mV/V. The threshold voltage is determined at this current (10 -7 x (W/L)). Channel length of MOSFET increases then DIBL decreases. It has been observed that DIBL value is improve at gate oxide thickness is 3nm and SS value is 60 mV/decade at doping density 1.1x10 19 cm -3 . Table  4 shows that DIBL value at different oxide thicknes at tsi=10nm, ND=9x10 18 cm -3 , L=100nm and DIBL value at different channel length at tsi=10nm, tox=3nm and ND=9x10 18 cm -3 .   Table 5 shows that comparison of proposed device values with different researchers proposed MOSFETs at tox=7nm, tsi=10nm, ND=1x10 19 cm -3 and L=1000nm. It has been observed that on current of proposed device is maximum and off current is minimum (1pA at channel length 120nm) which means that Ion/Ioff ratio improves compares to single material double gate junctionless transistor. Subthreshold slope of our device is minimum compare to [11] dual material double gate junctionless transistor. Threshold voltage of my proposed device and other researcher's device mentined in references is approximately same [21] [22].

CONCLUSION
In this paper, we have proposed, model of bulk current for long channel Dual Material Double gate junctionless MOSFET from Poisson equation in the channel using a depletion approximation and has been verified by simulation result of cogenda visual TCAD. Model is valid in all regions, sub-threshold, linear and saturation. In this paper we observe that MOSFET channel thickness, oxide thickness; channel doping and channel length affect on drain current and threshold voltage of MOSFET. It has been observed that current driving capability of MOSFET is improved due to Dual material gate. Therefore this device is a better candidate for operating in the three regions.