A Novel Design and Implementation of FBMC Transceiver for Low Power Applications

Mohamed Saber Elsayes


Filter Bank Multicarrier (FBMC) communication system has a complex structure since it depends on polyphase filter bank; which consists of fast Fourier Transform/ Inverse Fast Fourier Transform (FFT/IFFT) processors and a filter bank of Finite Impulse Response (FIR) filters. This paper presents, analyzes, and implements a new design of FBMC transceiver which removes the polyphase filter completely in both transmitter and receiver and uses instead of it, a multi-level cascaded structure of FIR subfilters in which, the number of levels depends on the number of subscribers or subchannels. The coefficients of each subfilter in the structure are chosen using an optimization algorithm to minimize the amplitude of sidelobes compared to the amplitude of the main lobe in the frequency response of the subfilter. The proposed design reduces the number of multiplications compared to the conventional design by 65%. The proposed, and conventional FBMC transceiver are implemented using Field Programmable Gate array (FPGA) Xilinx Spartan-6 SLX45FGG484-3, implementation results indicate that the proposed architecture, saves 24% of resources of FPGA board, works faster, and saves 27% of power consumption compared to conventional FBMC transceiver.


FBMC, Polyphase filter, FPGA


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Indonesian Journal of Electrical Engineering and Informatics (IJEEI)
ISSN 2089-3272

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This work is licensed under a Creative Commons Attribution 4.0 International License.

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