Design and Analysis of High Gain Low Power CMOS Comparator

Labonnah Farzana Rahman, Mamun Bin Ibne Reaz, Wan Irma Idayu Restu, Mohammad Marufuzzaman, Lariyah Mohd Sidek

Abstract


The comparator is the most significant component of the analog-to-digital converter, voltage regulator, switching circuits, communication blocks etc. Depending on the various design schemes, comparator performance varied upon target applications. At present, low power, high gain, area efficient and high-speed comparator designed methods are necessary for complementary metal oxide semiconductor (CMOS) industry. In this research, a low power and high gain CMOS comparator are presented which utilized two-stage differential input stages with replication of DC current source to achieve higher gain, higher phase margin, higher bandwidth, and lower power consumption. The simulated results showed that, by using a minimum power supply of 1.2 V, the comparator could generate higher gain 77.45 dB with a phase margin of 60.08°. Moreover, the modified design consumed only 2.84 µW of power with a gain bandwidth of 30.975 MHz. In addition, the chip layout area of the modified comparator is found only 0.0033 mm2.


Keywords


CMOS, two-stage, comparator, high gain, low power.

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Indonesian Journal of Electrical Engineering and Informatics (IJEEI)
ISSN 2089-3272

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This work is licensed under a Creative Commons Attribution 4.0 International License.

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