Efficient Dual Mode Arbitration Scheme for Multiprocessor Hardware Interface in System-on-Chip

Abstract

A processor transforms human needs into hardware operations in any SoC. The single processor was ubiquitous in previous systems. But as chip size, complexity, and speed increase, several processors are used nowadays to handle concurrent operations. To manage requests from several processors, a central hardware block will conduct the arbitration among the processors and allow a processor to access the bus. This paper addresses the multiprocessor arbitration in any System on Chip or ASIC. There are several arbitration algorithms  available in the realm of technology, and any system can choose a specific arbitration to implement in hardware based on its own demands. Instead of using one type of arbitration in hardware, this research combined and used two schemes and implemented both possibilities in a hardware dual-mode arbiter system to be used in SoC. The proposed dual-mode arbiter was initially hardware modeled using Verilog HDL, then functionalities were verified using industry simulator Cadence and Modelsim, and finally synthesized and implemented using Xilinx XST EDA tool and FPGA device.   The AMBA, the industry-standard bus protocol, is being considered for the master processors and the proposed dual-mode arbiter to ensure an efficient hardware interface and to use with any off-the-shelf macro available for the high-tech industry.