An Adjacent Gray Code Pairing Approach for Fault Identification in Reversible Circuits

Authors

Dimpimoni Kalita
Assam University image/svg+xml
Mousum Handique
Assam University image/svg+xml
DOI: https://doi.org/10.52549/ijeei.v13i4.7097
Download PDF
Published: 25-11-2025 • Issue: Vol. 13 No. 4: December 2025 • Section: Regular paper

Abstract

The classical computing works on the concept of irreversibility increasing the heat dissipation in computing machinery. The remarkable ability of reversible computing is to reduce this dissipation of heat and to generate lossless information. The reversible circuit is the way to implement the reversible function. Therefore, the perfection of the functional behavior of the circuit plays a vital part within the realm of testing. Occurrence of faults in the reversible circuits creates a dysfunctional behavior in the circuit. Here in this study, a fault detection approach has been devised for reversible circuits that effectively identifies all categories of Missing Gate Faults (MGFs), such as single, multiple, partial, and repeated gate faults, through the use of the Adjacent Gray Code Pairing (AGCP) technique. The approach includes a process of conversion of binary to gray codes and pairing of non duplicative consecutive adjacent codes by which test vectors can be achieved for finding the respective faults with a 50\% reduction in test set size. An experimental study and comparative analysis with existing methods have been carried out using a variety of standard reversible circuits.
Keywords: Reversible Circuit; Fault Models; Missing Gate Fault; Test Vector; Adjacent Gray Code Pairing

References

REFERENCES

G. E. Moore, “Cramming more components onto integrated circuits,†Proceedings of the IEEE, vol. 86, no. 1, pp. 82–85, 1998.

H. F. Chau and H. K. Lo, “One-way functions in reversible computations,†Cryptologia, vol. 21, no. 2, pp. 139–148, 1997.

R. Landauer, “Irreversibility and heat generation in the computing process,†IBM journal of research and development, vol. 5, no. 3, pp. 183–191, 1961.

C. H. Bennett, “Logical reversibility of computation,†IBM journal of Research and Development, vol. 17, no. 6, pp. 525–532, 1973.

M. B. Plenio and V. Vitelli, “The physics of forgetting: Landauer’s erasure principle and information theory,†Contemporary Physics, vol. 42, no. 1, pp. 25–60, 2001.

M. P. Frank, “The physical limits of computing,†Computing in Science & Engineering, vol. 4, no. 3, pp. 16–26, 2002.

A. Sarker, H. M. Hasan Babu, and S. M. M. Rashid, “Design of a dna-based reversible arithmetic and logic unit,†IET nanobiotechnology, vol. 9, no. 4, pp. 226–238, 2015.

M. Sarkar, P. Ghosal, and S. P. Mohanty, “Minimal reversible circuit synthesis on a dna computer,†Natural Computing, vol. 16, pp. 463–472, 2017.

M. Rofail and A. Younes, “Synthesis strategy of reversible circuits on dna computers,†Symmetry, vol. 13, no. 7, p. 1242, 2021.

S. Kotiyal, H. Thapliyal, and N. Ranganathan, “Design of reversible adder-subtractor and its mapping in optical computing domain,†in transactions on Computational Science XXIV: Special Issue on Reversible Computing. Springer, 2014, pp. 37–55.

D. G. S. Rao, S. Swarnakar, and S. Kumar, “Design of all-optical reversible logic gates using photonic crystal waveguides for optical computing and photonic integrated circuits,†Applied Optics, vol. 59, no. 35, pp. 11 003–11 012, 2020.

H. Thapliyal and M. Zwolinski, “Reversible logic to cryptographic hardware: a new paradigm,†in 2006 49th IEEE International Midwest Symposium on Circuits and Systems, vol. 1. IEEE, 2006, pp. 342–346.

V. Raj, S. Janakiraman, S. Rajagopalan, and R. Amirtharajan, “Security analysis of reversible logic cryptography design with lfsr key on 32-bit microcontroller,†Microprocessors and Microsystems, vol. 84, p. 104265, 2021.

X. Ma, J. Huang, C. Metra, and F. Lombardi, “Reversible gates and testability of one dimensional arrays of molecular qca,†Journal of Electronic Testing, vol. 24, pp. 297–311, 2008.

T. N. Sasamal, A. K. Singh, and A. Mohan, “Efficient design of reversible alu in quantum-dot cellular automata,†Optik, vol. 127, no. 15, pp. 6172–6182, 2016.

M. Perkowski, P. Kerntopf, A. Buller, M. Chrzanowska-Jeske, A. Mishchenko, X. Song, A. Al-Rabadi, L. Jezwiak, A. Coppola, and B. Massey, “Regular realization of symmetric functions using reversible logic,†in Proceedings Euromicro Symposium on Digital Systems Design. IEEE, 2001, pp. 245–252.

A. JavadiAbhari, S. Patil, D. Kudrow, J. Heckey, A. Lvov, F. T. Chong, and M. Martonosi, “Scaffcc: A framework for compilation and analysis of quantum computing programs,†in Proceedings of the 11th ACM Conference on Computing Frontiers, 2014, pp. 1–10.

O. Oumarou, A. Paler, and R. Basmadjian, “Quantify: A framework for resource analysis and design verification of quantum circuits,†in 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2020, pp. 126–131.

M. Arabzadeh, M. Saheb Zamani, M. Sedighi, and M. Saeedi, “Depth-optimized reversible circuit synthesis,†Quantum information processing, vol. 12, pp. 1677–1699, 2013.

M. Mohammadi and M. Eshghi, “Heuristic methods to use don’t cares in automated design of reversible and quantum logic circuits,†Quantum Information Processing, vol. 7, pp. 175–192, 2008.

R. Montaser, A. Younes, and M. Abdel-Aty, “Improving the quantum cost of nct-based reversible circuit,†Quantum Information Processing, vol. 14, pp. 1249–1263, 2015.

K. Datta, G. Rathi, I. Sengupta, and H. Rahaman, “Exact synthesis of reversible circuits using a* algorithm,†Journal of The Institution of Engineers (India): Series B, vol. 96, pp. 121–130, 2015.

H. Jayashree, H. Thapliyal, H. R. Arabnia, and V. K. Agrawal, “Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier,†The Journal of Supercomputing, vol. 72, pp. 1477–1493, 2016.

H. M. Gaur, A. K. Singh, and U. Ghanekar, “Offline testing of reversible logic circuits: an analysis,†Integration, vol. 62, pp. 50–67, 2018.

M. Abramovici, M. A. Breuer, A. D. Friedman et al., Digital systems testing and testable design. Computer science press New York, 1990, vol. 2.

K. N. Patel, J. P. Hayes, and I. L. Markov, “Fault testing for reversible circuits,†IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 8, pp. 1220–1230, 2004.

M. Ibrahim, A. R. Chowdhury, and H. M. H. Babu, “Minimization of cts of k-cnot circuits for ssf and msf model,†in 2008 IEEE international symposium on defect and fault tolerance of VLSI systems. IEEE, 2008, pp. 290–298.

M. Handique, J. K. Deka, S. Biswas, and K. Dutta, “Minimal test set generation for input stuck-at and bridging faults in reversible circuits,†in TENCON 2017-2017 IEEE Region 10 Conference. IEEE, 2017,

pp. 234–239.

H. M. Gaur, A. K. Singh, and U. Ghanekar, “Design for stuck-at fault testability in multiple controlled toffoli-based reversible circuits.†Defence Science Journal, vol. 68, no. 4, 2018.

H. Rahaman, D. K. K. D. K. Kole, D. K. Das, and B. B. Bhattacharya, “Optimum test set for bridging fault detection in reversible circuits,†in 16th Asian test symposium (ATS 2007). IEEE, 2007, pp. 125–128.

P. Sarkar and S. Chakrabarti, “Universal test set for bridging fault detection in reversible circuit,†in 2008 3rd international design and test workshop. IEEE, 2008, pp. 51–56.

I. Hayes, John P and and B. Becker, “Testing for missing-gate faults in reversible circuits,†in 13th Asian test symposium. IEEE, 2004, pp. 100–105.

A. Kole, R. Wille, K. Datta, and I. Sengupta, “Test pattern generation effort evaluation of reversible circuits,†in Reversible Computation: 9th International Conference, RC 2017, Kolkata, India, July 6-7, 2017, Proceedings 9. Springer, 2017, pp. 162–175.

I. Polian, T. Fiehn, B. Becker, and J. P. Hayes, “A family of logical fault models for reversible circuits,†in 14th Asian Test Symposium (ATS’05). IEEE, 2005, pp. 422–427.

M. Handique and H. K. Sarma, “Testable design for positive control flipping faults in reversible circuits,†Indonesian Journal of Electrical Engineering and Informatics (IJEEI), vol. 11, no. 2, pp. 416–430, 2023.

J. Rice, “An overview of fault models and testing approaches for reversible logic,†in 2013 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM). IEEE, 2013, pp. 125–130.

D. P. Vasudevan, P. K. Lala, J. Di, and J. P. Parkerson, “Reversible-logic design with online testability,†IEEE transactions on instrumentation and measurement, vol. 55, no. 2, pp. 406–414, 2006.

M. Zamani and M. B. Tahoori, “Online missing/repeated gate faults detection in reversible circuits,†in 2011 IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems.

IEEE, 2011, pp. 435–442.

T. Toffoli, “Reversible computing,†in International colloquium on automata, languages, and programming. Springer, 1980, pp. 632–644.

R. P. Feynman and T. Hey, “Quantum mechanical computers,†in Feynman Lectures on Computation. CRC Press, 2023, pp. 169–192.

B. Mondal, P. Das, P. Sarkar, and S. Chakraborty, “A comprehensive fault diagnosis technique for reversible logic circuits,†Computers & Electrical Engineering, vol. 40, no. 7, pp. 2259–2272, 2014.

M. A. Nielsen and I. L. Chuang, “Quantum computation and quantum information,†Phys. Today, vol. 54, no. 2, p. 60, 2001.

H. Rahaman, D. K. Kole, D. K. Das, and B. B. Bhattacharya, “On the detection of missing-gate faults in reversible circuits by a universal test set,†in 21st international conference on VLSI design (VLSID 2008). IEEE, 2008, pp. 163–168.

H. Zhang, S. Frehse, R. Wille, and R. Drechsler, “Determining minimal testsets for reversible circuits using boolean satisfiability,†in IEEE Africon’11. IEEE, 2011, pp. 1–6.

R. Wille, H. Zhang, and R. Drechsler, “Atpg for reversible circuits using simulation, boolean satisfiability, and pseudo boolean optimization,†in 2011 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2011, pp. 120–125.

M. Zamani, M. B. Tahoori, and K. Chakrabarty, “Ping-pong test: Compact test vector generation for reversible circuits,†in 2012 IEEE 30th VLSI Test Symposium (VTS). IEEE, 2012, pp. 164–169.

A. P. Surhonne, A. Chattopadhyay, and R. Wille, “Automatic test pattern generation for multiple missing gate faults in reversible circuits: Work in progress report,†in Reversible Computation: 9th International Conference, RC 2017, Kolkata, India, July 6-7, 2017, Proceedings 9. Springer, 2017, pp. 176–182.

D. Kheirandish, M. Haghparast, M. Reshadi, and M. Hosseinzadeh, “Efficient techniques for fault detection and location of multiple controlled toffoli-based reversible circuit,†Quantum Information Processing, vol. 20, no. 11, p. 370, 2021.

B. Mondal, C. Bandyopadhyay, A. Bhattacharjee, D. Roy, S. Parekh, and H. Rahaman, “An approach for detection and localization of missing gate faults in reversible circuit,†IETE Journal of Research, vol. 68, no. 5, pp. 3607–3627, 2022.

D. Maslov, “Reversible logic synthesis benchmarks page (2015), online: http://webhome.cs.uvic.ca/dmaslov/"

R. Wille, D. Große, L. Teuber, G. W. Dueck, and R. Drechsler, “Revlib: An online resource for reversible functions and reversible circuits,†in 38th International Symposium on Multiple Valued Logic (ismvl 2008). IEEE, 2008, pp. 220–225.

Author Biographies

Dimpimoni Kalita
Research Scholar, Department of Computer Science and Engineering, TSSOT, Assam University, Silchar-788011, Assam, India
Mousum Handique
Associate Professor, Department of Computer Science and Engineering, TSSOT, Assam University, Silchar-788011, Assam, India

How to Cite

[1]
D. Kalita and M. Handique, “An Adjacent Gray Code Pairing Approach for Fault Identification in Reversible Circuits”, IJEEI, vol. 13, no. 4, pp. 856–872, Nov. 2025, doi: 10.52549/ijeei.v13i4.7097.