Testable Design for Positive Control Flipping Faults in Reversible Circuits

Mousum Handique, Hiren K D Sarma

Abstract


Fast computational power is a major concern in every computing system. The advancement of the fabrication process in the present semiconductor technologies provides to accommodate millions of gates per chip and is also capable of reducing the size of the chips. Concurrently, the complex circuit design always leads to high power dissipation and increases the fault rates. Due to these difficulties, researchers explore the reversible logic circuit as an alternative way to implement the low-power circuit design. It is also widely applied in recent technology trends like quantum computing. Analyzing the correct functional behavior of these circuits is an essential requirement in the testing of the circuit. This paper presents a testable design for the k-CNOT based circuit capable of diagnosing the Positive Control Flipping Faults (PCFFs) in reversible circuits. The proposed work shows that generating a single test vector that applies to the constructed design circuit is sufficient for covering the PCFFs in the reversible circuit. Further, the parity-bit operations are augmented to the constructed testable circuit that produces the parity-test pattern to extract the faulty gate location of PCFFs. Various reversible benchmark circuits are used for evaluating the experimental results to establish the correctness of the proposed fault diagnosis technique. Also a comparative analysis is performed with the existing work.

Keywords


Reversible logic circuit; Test vector; Testable design circuit; Parity-test pattern; Positive control flipping faults

References


A. B´erut, A. Arakelyan, A. Petrosyan, S. Ciliberto, R. Dillenschneider and E. Lutz, “Experimental verification of landauerâs principle linking information and thermodynamics,” Nature., vol. 483, no. 7388, pp. 187–189, 2012.

R. Wille, R. Drechsler, C. Osewold and A. Ortiz, "Automatic design of low-poer encoders using reversible circuit synthesis," in 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2012, pp. 1036–1041.

M. A. Nielsen and I. L. Chuang, Quantum Computation and Quantum Information: 10th Anniversary Edition,10th ed. New York, NY, USA: Cambridge University Press, 2011.

O. Oumarou, A. Paler and R. Basmadjian, "Quantify: A framework for resource analysis and design verification of quantum circuits,"in 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, 2020pp. 126-131.

C. Taraphdar, T. Chattopadhyay and J. N. Roy, "Mach-zehnder interferometer-based all-optical reversible logic gate,"Optics & Laser Technology., vol. 42, no. 2, pp. 249–259, 2010.

M, Rofail and A. Younes, "A. Synthesis strategy of reversible circuits on dna computers,"Symmetry., vol.13, no. 7, p. 1242, 2021.

X. Ma, J. Huang, C. Metra and F. Lombardi, “Reversible gates and testability of one dimensional arrays of molecular qca,”Journal of Electronic Testing, vol. 24, no. 1, pp. 297–311, 2008.

R. Landauer, “Irreversibility and heat generation in the computation process,”IBM Journal of Research and Development, vol. 5, no. 3, pp. 183–191, 1961.

C. H. Bennett, “Logical reversibility of computation,” IBM Journal of Research and Development, vol. 17, no. 6, pp. 525–532, Nov. 1973.

Y. V. Rentergem and A. De Vos, “Optimal design of a reversible full adder,” 2005.

M. K. Thomsen and R.Glück, “Optimized reversible binary coded decimal adders,”Journal of Systems Architecture,vol. 54, no. 7, pp. 697–706, 2008.

M. Szyprowski and P. Kerntopf, “Reducing quantum cost in reversible toffoli circuits,” arXiv preprint arXiv: 1105.5831, 2011.

D. Maslov, “Reversible logic synthesis benchmarks page (2015),” online: http://webhome.cs.uvic.ca/dmaslov/.

B. Desoete, A. De Vos, M. Sibinski, and T. Widerski, “Feynman’s reversible logic gates, implemented in silicon,” 1999.

B. Desoete and A. De Vos, “A reversible carry-look-ahead adder using control gates,” Integration., vol. 33, no. 1-2, pp. 89–104, 2002.

A. De Vos and Y. V. Rentergem., “Reversible computing: from mathematical group theory to electronical circuit experiment,” in Proceedings of the 2nd Conference on Computing Frontiers, pp. 35–44, 2005.

V. V. Shende, A. K Prasad, I. L Markov, and J. P Hayes, “Synthesis of reversible logic circuits,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 710–722, 2003.

Y. V. Rentergem and A. De Vos, “Synthesis and optimization of reversible circuits,” 2007.

N. M Nayeem and J. E Rice, “Improved esop-based synthesis of reversible logic,” in Reed-Muller Workshop, 2011.

N. K. Jha and S. Gupta, Testing of digital systems (pp. I-Vi), Cambridge: Cambridge University Press, 2003.

J. Rice, "An overview of fault models and testing approaches for reversible logic," in 2013 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM).IEEE, 2013, pp. 125–130.

K. N. Patel, J. P. Hayes and I. L. Markov, "Fault testing for reversible circuits,"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 8, pp. 1220-1230, 2004.

J. P. Hayes, I. Polian and B. Becker, “Testing for missing-gate faults in reversible circuits,” in 13th Asian Test Symposium, IEEE, 2004, pp. 100–105.

I. Polian, T. Fiehn, B. Becker and J. P. Hayes, "A family of logical fault models for reversible circuits," in 14th Asian Test Symposium (ATS’05). IEEE, 2005, pp. 422-427.

R. Wille, H. Zhang, R. Drechsler, “Atpg for reversible circuits using simulation, boolean satisfiability, and pseudo boolean optimization,”in 2011 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2011, pp. 120–125.

A.N. Nagamani, S. Ashwin, B. Abhishek, and V. K. Agrawal, “An exact approach for complete test set generation of toffoli-fredkin-peres based reversible circuits,” Journal of Electronic Testing, vol. 32, no. 2, pp. 175–196, 2016.

A.N Nagamani, S.N Anuktha, N. Nanditha, and V. K. Agrawal, “A genetic algorithm-based heuristic method for test set generation in reversible circuits.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 2, pp. 324–336, 2017.

M. Handique, J. K. Deka, and S. Biswas, “An efficient test set construction scheme for multiple missing-gate faults in reversible circuits.” Journal of Electronic Testing, vol. 36, pp. 105–122, 2020.

M. Handique, J. K. Deka, and S. Biswas, “Fault localization scheme for missing gate faults in reversible circuits.” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 27, no. 4, pp. 1–29, 2022.

H. Rahaman, D. K. Kole, D. K. Das and B. B. Bhattacharya, "Fault diagnosis in reversible circuits under missing-gate fault model,"Computers & Electrical Engineering, vol. 37, no. 4, pp. 475–485, 2011.

T. Toffoli, "Reversible computing," in International Colloquium on Automata, Languages, and Programming. Springer, Berlin, Heidelberg, 1980, pp. 632–644.

R. P. Feynman, “Quantum mechanical computers,” Foundations of physics, vol. 16, no. 6, pp. 507–531, 1986.

H. Rahaman, D. K. Kole, D. K. Das and B. B. Bhattacharya, "Optimum test set for bridging fault detection in reversible circuits," in 16th Asian Test Symposium (ATS 2007). IEEE, 2007, pp. 125–128.

J. Zhong and J. C. Muzio, "Analyzing fault models for reversible logic circuits,"in 2006 IEEE international conference on evolutionary computation. IEEE, 2006, pp. 2422–2427.

M. Handique, A. Prasad and H. K. D. Sarma, “Complete test set generation for control flipping faults in reversible circuits,” in Contemporary Issues in Communication, Cloud and Big Data Analytics,Springer, Singapore, 2022, pp. 345–355.

M. Lukac, M. Kameyama, M. Perkowski, P. Kerntopf and C. Moraga, “Fault models in reversible and quantum circuits,” in Advances in Unconventional Computing, Springer Cham, pp. 475–493, 2017.

N. Nayeem and J. Rice, “A simple aaproach for designing online testable reversible circuits,” in Communication Computers and Signal Processing (PacRim), inIEEE Pacific Rim Conference on communications, computers and signal processing,IEEE, 2011, pp. 85–90.

B. Mondal, P. Das, P. Sarkar and S. Chakraborty, “A comprehensive fault diagnosis technique for reversible logic circuits,”Computers & Electrical Engineering, vol. 40, no. 7, pp. 2259–2272, 2014.

H. M. Gaur, A. K. Singh and U. A. Ghanekar, “A new dft methodology for k-CNOT reversible circuits and its implementation using quantum-dot cellular automata,” Optik,vol. 127, no. 22,pp. 10593–10601, 2016.

B. Mondal, C. Bandyopadhyay, A. Bhattacharjee, D. Roy, S. Parekh and H. Rahaman, “An aaproach for fault detection and localization of missing gate faults in reversible circuits,” IETE Journal of Research, pp. 1–21, 2020.

J. Mondal, A. Deb and D. K. Das, “An efficient design for testability approach of reversible logic circuits,” Journal of Circuits, Systems and Computers, vol. 30, no. 6:2150094, 2021

D. Kheirandish, M. Haghparast, M. Reshadi and M. Hosseinzadeh., “Efficient techniques for fault detection and location of multiple controlled toffoli-based reversible circuit,” Quantum Information Processing, vol. 20, no. 11:370, 2021.

R. Wille, D. Große, L. Teuber, G. W. Dueck and R. Drechsler, "Revlib: An online resource for reversible functions and reversible circuits," in 38th International Symposium on Multiple Valued Logic (ismvl 2008). IEEE, 2008, pp. 220–225.


Full Text: PDF

Refbacks

  • There are currently no refbacks.


 

Indonesian Journal of Electrical Engineering and Informatics (IJEEI)
ISSN 2089-3272

Creative Commons Licence

This work is licensed under a Creative Commons Attribution 4.0 International License.

web analytics
View IJEEI Stats

Error. Page cannot be displayed. Please contact your service provider for more details. (11)