Effect of clock gating in conditional pulse enhancement flip-flop for low power applications

Kuruvilla John, Vinod Kumar R. S., Kumar S. S.


Flip-Flops (FFs) play a fundamental role in digital designs. A clock system consumes above 25% of total system power. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. This flip-flop architecture is embedded with two key features. Firstly, the enhancement in width and height of triggering pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90-nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. Its maximum power saving against conventional designs is up to 30.65%.


Clock gating; Conditional discharging; Implicit Low power; Pulse flip-flop

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Indonesian Journal of Electrical Engineering and Informatics (IJEEI)
ISSN 2089-3272

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This work is licensed under a Creative Commons Attribution 4.0 International License.

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